To Verify expertise chip and blocklevel from spec to tape out for complex designs. Test Plans bench and infrastructure test cases and more task should be known by a user for multiple projects.
Experience: 0-5 years
Education: Any Graudate/PG
Sal: As per Company Rules
Hands on experience in sys verilog, specman/vera or C++ knowledge of CPU architecture, system level awareness integration and initilization bring DFT knowledge is huge plus poing, must be excellent planning skills and motivation is must, for various functional domain and methodologies.
Tag : Banglore